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858 lines
21 KiB
858 lines
21 KiB
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#ifndef _GETSET_H_
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#define _GETSET_H_
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#include "cpuexec.h"
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#include "dsp.h"
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#include "sa1.h"
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#include "spc7110.h"
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#include "c4.h"
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#include "obc1.h"
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#include "seta.h"
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#include "bsx.h"
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#include "msu1.h"
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#define addCyclesInMemoryAccess \
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if (!CPU.InDMAorHDMA) \
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{ \
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CPU.Cycles += speed; \
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while (CPU.Cycles >= CPU.NextEvent) \
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S9xDoHEventProcessing(); \
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}
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#define addCyclesInMemoryAccess_x2 \
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if (!CPU.InDMAorHDMA) \
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{ \
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CPU.Cycles += speed << 1; \
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while (CPU.Cycles >= CPU.NextEvent) \
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S9xDoHEventProcessing(); \
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}
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extern uint8 OpenBus;
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static inline int32 memory_speed (uint32 address)
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{
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if (address & 0x408000)
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{
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if (address & 0x800000)
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return (CPU.FastROMSpeed);
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return (SLOW_ONE_CYCLE);
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}
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if ((address + 0x6000) & 0x4000)
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return (SLOW_ONE_CYCLE);
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if ((address - 0x4000) & 0x7e00)
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return (ONE_CYCLE);
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return (TWO_CYCLES);
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}
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inline uint8 S9xGetByte (uint32 Address)
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{
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int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
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uint8 *GetAddress = Memory.Map[block];
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int32 speed = memory_speed(Address);
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uint8 byte;
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if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
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{
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byte = *(GetAddress + (Address & 0xffff));
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addCyclesInMemoryAccess;
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return (byte);
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}
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switch ((pint) GetAddress)
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{
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case CMemory::MAP_CPU:
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byte = S9xGetCPU(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_PPU:
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if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
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return (OpenBus);
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byte = S9xGetPPU(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_LOROM_SRAM:
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case CMemory::MAP_SA1RAM:
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// Address & 0x7fff : offset into bank
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// Address & 0xff0000 : bank
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// bank >> 1 | offset : SRAM address, unbound
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// unbound & SRAMMask : SRAM offset
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byte = *(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_LOROM_SRAM_B:
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byte = *(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB));
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_HIROM_SRAM:
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case CMemory::MAP_RONLY_SRAM:
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byte = *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask));
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_BWRAM:
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byte = *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000));
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_DSP:
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byte = S9xGetDSP(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_SPC7110_ROM:
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byte = S9xGetSPC7110Byte(Address);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_SPC7110_DRAM:
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byte = S9xGetSPC7110(0x4800);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_C4:
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byte = S9xGetC4(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_OBC_RAM:
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byte = S9xGetOBC1(Address & 0xffff);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_SETA_DSP:
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byte = S9xGetSetaDSP(Address);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_SETA_RISC:
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byte = S9xGetST018(Address);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_BSX:
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byte = S9xGetBSX(Address);
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addCyclesInMemoryAccess;
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return (byte);
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case CMemory::MAP_NONE:
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default:
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byte = OpenBus;
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addCyclesInMemoryAccess;
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return (byte);
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}
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}
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inline uint16 S9xGetWord (uint32 Address, enum s9xwrap_t w = WRAP_NONE)
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{
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uint16 word;
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uint32 mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
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if ((Address & mask) == mask)
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{
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PC_t a;
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word = OpenBus = S9xGetByte(Address);
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switch (w)
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{
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case WRAP_PAGE:
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a.xPBPC = Address;
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a.B.xPCl++;
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return (word | (S9xGetByte(a.xPBPC) << 8));
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case WRAP_BANK:
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a.xPBPC = Address;
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a.W.xPC++;
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return (word | (S9xGetByte(a.xPBPC) << 8));
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case WRAP_NONE:
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default:
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return (word | (S9xGetByte(Address + 1) << 8));
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}
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}
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int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
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uint8 *GetAddress = Memory.Map[block];
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int32 speed = memory_speed(Address);
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if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
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{
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word = READ_WORD(GetAddress + (Address & 0xffff));
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addCyclesInMemoryAccess_x2;
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return (word);
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}
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switch ((pint) GetAddress)
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{
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case CMemory::MAP_CPU:
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word = S9xGetCPU(Address & 0xffff);
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addCyclesInMemoryAccess;
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word |= S9xGetCPU((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_PPU:
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if (CPU.InDMAorHDMA)
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{
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word = OpenBus = S9xGetByte(Address);
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return (word | (S9xGetByte(Address + 1) << 8));
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}
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word = S9xGetPPU(Address & 0xffff);
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addCyclesInMemoryAccess;
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word |= S9xGetPPU((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_LOROM_SRAM:
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case CMemory::MAP_SA1RAM:
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if (Memory.SRAMMask >= MEMMAP_MASK)
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word = READ_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
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else
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word = (*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask))) |
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((*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask))) << 8);
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addCyclesInMemoryAccess_x2;
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return (word);
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case CMemory::MAP_LOROM_SRAM_B:
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if (Multi.sramMaskB >= MEMMAP_MASK)
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word = READ_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB));
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else
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word = (*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB))) |
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((*(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB))) << 8);
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addCyclesInMemoryAccess_x2;
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return (word);
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case CMemory::MAP_HIROM_SRAM:
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case CMemory::MAP_RONLY_SRAM:
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if (Memory.SRAMMask >= MEMMAP_MASK)
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word = READ_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask));
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else
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word = (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask)) |
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(*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0x1f0000) >> 3)) & Memory.SRAMMask)) << 8));
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addCyclesInMemoryAccess_x2;
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return (word);
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case CMemory::MAP_BWRAM:
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word = READ_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000));
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addCyclesInMemoryAccess_x2;
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return (word);
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case CMemory::MAP_DSP:
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word = S9xGetDSP(Address & 0xffff);
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addCyclesInMemoryAccess;
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word |= S9xGetDSP((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_SPC7110_ROM:
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word = S9xGetSPC7110Byte(Address);
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addCyclesInMemoryAccess;
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word |= S9xGetSPC7110Byte(Address + 1) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_SPC7110_DRAM:
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word = S9xGetSPC7110(0x4800);
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addCyclesInMemoryAccess;
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word |= S9xGetSPC7110(0x4800) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_C4:
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word = S9xGetC4(Address & 0xffff);
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addCyclesInMemoryAccess;
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word |= S9xGetC4((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_OBC_RAM:
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word = S9xGetOBC1(Address & 0xffff);
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addCyclesInMemoryAccess;
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word |= S9xGetOBC1((Address + 1) & 0xffff) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_SETA_DSP:
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word = S9xGetSetaDSP(Address);
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addCyclesInMemoryAccess;
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word |= S9xGetSetaDSP(Address + 1) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_SETA_RISC:
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word = S9xGetST018(Address);
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addCyclesInMemoryAccess;
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word |= S9xGetST018(Address + 1) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_BSX:
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word = S9xGetBSX(Address);
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addCyclesInMemoryAccess;
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word |= S9xGetBSX(Address + 1) << 8;
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addCyclesInMemoryAccess;
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return (word);
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case CMemory::MAP_NONE:
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default:
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word = OpenBus | (OpenBus << 8);
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addCyclesInMemoryAccess_x2;
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return (word);
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}
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}
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inline void S9xSetByte (uint8 Byte, uint32 Address)
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{
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int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
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uint8 *SetAddress = Memory.WriteMap[block];
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int32 speed = memory_speed(Address);
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if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
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{
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*(SetAddress + (Address & 0xffff)) = Byte;
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addCyclesInMemoryAccess;
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return;
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}
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switch ((pint) SetAddress)
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{
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case CMemory::MAP_CPU:
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S9xSetCPU(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_PPU:
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if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100)
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return;
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S9xSetPPU(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_LOROM_SRAM:
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if (Memory.SRAMMask)
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{
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*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = Byte;
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CPU.SRAMModified = TRUE;
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}
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_LOROM_SRAM_B:
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if (Multi.sramMaskB)
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{
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*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = Byte;
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CPU.SRAMModified = TRUE;
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}
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_HIROM_SRAM:
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if (Memory.SRAMMask)
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{
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*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask)) = Byte;
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CPU.SRAMModified = TRUE;
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}
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_BWRAM:
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*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte;
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CPU.SRAMModified = TRUE;
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_SA1RAM:
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*(Memory.SRAM + (Address & 0xffff)) = Byte;
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_DSP:
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S9xSetDSP(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_C4:
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S9xSetC4(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_OBC_RAM:
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S9xSetOBC1(Byte, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_SETA_DSP:
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S9xSetSetaDSP(Byte, Address);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_SETA_RISC:
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S9xSetST018(Byte, Address);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_BSX:
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S9xSetBSX(Byte, Address);
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addCyclesInMemoryAccess;
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return;
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case CMemory::MAP_NONE:
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default:
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addCyclesInMemoryAccess;
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return;
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}
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}
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inline void S9xSetWord (uint16 Word, uint32 Address, enum s9xwrap_t w = WRAP_NONE, enum s9xwriteorder_t o = WRITE_01)
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{
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uint32 mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff));
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if ((Address & mask) == mask)
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{
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PC_t a;
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if (!o)
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S9xSetByte((uint8) Word, Address);
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switch (w)
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{
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case WRAP_PAGE:
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a.xPBPC = Address;
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a.B.xPCl++;
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S9xSetByte(Word >> 8, a.xPBPC);
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break;
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case WRAP_BANK:
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a.xPBPC = Address;
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a.W.xPC++;
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S9xSetByte(Word >> 8, a.xPBPC);
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break;
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case WRAP_NONE:
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default:
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S9xSetByte(Word >> 8, Address + 1);
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break;
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}
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if (o)
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S9xSetByte((uint8) Word, Address);
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return;
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}
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int block = (Address & 0xffffff) >> MEMMAP_SHIFT;
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uint8 *SetAddress = Memory.WriteMap[block];
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int32 speed = memory_speed(Address);
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if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
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{
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WRITE_WORD(SetAddress + (Address & 0xffff), Word);
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addCyclesInMemoryAccess_x2;
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return;
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}
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switch ((pint) SetAddress)
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{
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case CMemory::MAP_CPU:
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if (o)
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{
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S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
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addCyclesInMemoryAccess;
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S9xSetCPU((uint8) Word, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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}
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else
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{
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S9xSetCPU((uint8) Word, Address & 0xffff);
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addCyclesInMemoryAccess;
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S9xSetCPU(Word >> 8, (Address + 1) & 0xffff);
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addCyclesInMemoryAccess;
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return;
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}
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case CMemory::MAP_PPU:
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if (CPU.InDMAorHDMA)
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{
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if ((Address & 0xff00) != 0x2100)
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S9xSetPPU((uint8) Word, Address & 0xffff);
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if (((Address + 1) & 0xff00) != 0x2100)
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S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
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return;
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}
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if (o)
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{
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S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
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addCyclesInMemoryAccess;
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S9xSetPPU((uint8) Word, Address & 0xffff);
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addCyclesInMemoryAccess;
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return;
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}
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else
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{
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S9xSetPPU((uint8) Word, Address & 0xffff);
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addCyclesInMemoryAccess;
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S9xSetPPU(Word >> 8, (Address + 1) & 0xffff);
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addCyclesInMemoryAccess;
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return;
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}
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case CMemory::MAP_LOROM_SRAM:
|
|
if (Memory.SRAMMask)
|
|
{
|
|
if (Memory.SRAMMask >= MEMMAP_MASK)
|
|
WRITE_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask), Word);
|
|
else
|
|
{
|
|
*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = (uint8) Word;
|
|
*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask)) = Word >> 8;
|
|
}
|
|
|
|
CPU.SRAMModified = TRUE;
|
|
}
|
|
|
|
addCyclesInMemoryAccess_x2;
|
|
return;
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if (Multi.sramMaskB)
|
|
{
|
|
if (Multi.sramMaskB >= MEMMAP_MASK)
|
|
WRITE_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB), Word);
|
|
else
|
|
{
|
|
*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = (uint8) Word;
|
|
*(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB)) = Word >> 8;
|
|
}
|
|
|
|
CPU.SRAMModified = TRUE;
|
|
}
|
|
|
|
addCyclesInMemoryAccess_x2;
|
|
return;
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if (Memory.SRAMMask)
|
|
{
|
|
if (Memory.SRAMMask >= MEMMAP_MASK)
|
|
WRITE_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask), Word);
|
|
else
|
|
{
|
|
*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask)) = (uint8) Word;
|
|
*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0x1f0000) >> 3)) & Memory.SRAMMask)) = Word >> 8;
|
|
}
|
|
|
|
CPU.SRAMModified = TRUE;
|
|
}
|
|
|
|
addCyclesInMemoryAccess_x2;
|
|
return;
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
WRITE_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000), Word);
|
|
CPU.SRAMModified = TRUE;
|
|
addCyclesInMemoryAccess_x2;
|
|
return;
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
WRITE_WORD(Memory.SRAM + (Address & 0xffff), Word);
|
|
addCyclesInMemoryAccess_x2;
|
|
return;
|
|
|
|
case CMemory::MAP_DSP:
|
|
if (o)
|
|
{
|
|
S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetDSP((uint8) Word, Address & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
S9xSetDSP((uint8) Word, Address & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetDSP(Word >> 8, (Address + 1) & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
|
|
case CMemory::MAP_C4:
|
|
if (o)
|
|
{
|
|
S9xSetC4(Word >> 8, (Address + 1) & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetC4((uint8) Word, Address & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
S9xSetC4((uint8) Word, Address & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetC4(Word >> 8, (Address + 1) & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
if (o)
|
|
{
|
|
S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetOBC1((uint8) Word, Address & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
S9xSetOBC1((uint8) Word, Address & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
|
|
case CMemory::MAP_SETA_DSP:
|
|
if (o)
|
|
{
|
|
S9xSetSetaDSP(Word >> 8, Address + 1);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetSetaDSP((uint8) Word, Address);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
S9xSetSetaDSP((uint8) Word, Address);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetSetaDSP(Word >> 8, Address + 1);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
|
|
case CMemory::MAP_SETA_RISC:
|
|
if (o)
|
|
{
|
|
S9xSetST018(Word >> 8, Address + 1);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetST018((uint8) Word, Address);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
S9xSetST018((uint8) Word, Address);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetST018(Word >> 8, Address + 1);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
|
|
case CMemory::MAP_BSX:
|
|
if (o)
|
|
{
|
|
S9xSetBSX(Word >> 8, Address + 1);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetBSX((uint8) Word, Address);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
S9xSetBSX((uint8) Word, Address);
|
|
addCyclesInMemoryAccess;
|
|
S9xSetBSX(Word >> 8, Address + 1);
|
|
addCyclesInMemoryAccess;
|
|
return;
|
|
}
|
|
|
|
case CMemory::MAP_NONE:
|
|
default:
|
|
addCyclesInMemoryAccess_x2;
|
|
return;
|
|
}
|
|
}
|
|
|
|
inline void S9xSetPCBase (uint32 Address)
|
|
{
|
|
Registers.PBPC = Address & 0xffffff;
|
|
ICPU.ShiftedPB = Address & 0xff0000;
|
|
|
|
uint8 *GetAddress = Memory.Map[(int)((Address & 0xffffff) >> MEMMAP_SHIFT)];
|
|
|
|
CPU.MemSpeed = memory_speed(Address);
|
|
CPU.MemSpeedx2 = CPU.MemSpeed << 1;
|
|
|
|
if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
|
|
{
|
|
CPU.PCBase = GetAddress;
|
|
return;
|
|
}
|
|
|
|
switch ((pint) GetAddress)
|
|
{
|
|
case CMemory::MAP_LOROM_SRAM:
|
|
if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
|
|
CPU.PCBase = NULL;
|
|
else
|
|
CPU.PCBase = Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff);
|
|
return;
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
|
|
CPU.PCBase = NULL;
|
|
else
|
|
CPU.PCBase = Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff);
|
|
return;
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
|
|
CPU.PCBase = NULL;
|
|
else
|
|
CPU.PCBase = Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff);
|
|
return;
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
CPU.PCBase = Memory.BWRAM - 0x6000 - (Address & 0x8000);
|
|
return;
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
CPU.PCBase = Memory.SRAM;
|
|
return;
|
|
|
|
case CMemory::MAP_SPC7110_ROM:
|
|
CPU.PCBase = S9xGetBasePointerSPC7110(Address);
|
|
return;
|
|
|
|
case CMemory::MAP_C4:
|
|
CPU.PCBase = S9xGetBasePointerC4(Address & 0xffff);
|
|
return;
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
CPU.PCBase = S9xGetBasePointerOBC1(Address & 0xffff);
|
|
return;
|
|
|
|
case CMemory::MAP_BSX:
|
|
CPU.PCBase = S9xGetBasePointerBSX(Address);
|
|
return;
|
|
|
|
case CMemory::MAP_NONE:
|
|
default:
|
|
CPU.PCBase = NULL;
|
|
return;
|
|
}
|
|
}
|
|
|
|
inline uint8 * S9xGetBasePointer (uint32 Address)
|
|
{
|
|
uint8 *GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
|
|
|
|
if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
|
|
return (GetAddress);
|
|
|
|
switch ((pint) GetAddress)
|
|
{
|
|
case CMemory::MAP_LOROM_SRAM:
|
|
if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
|
|
return (NULL);
|
|
return (Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff));
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
|
|
return (NULL);
|
|
return (Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff));
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
|
|
return (NULL);
|
|
return (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff));
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
return (Memory.BWRAM - 0x6000 - (Address & 0x8000));
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
return (Memory.SRAM);
|
|
|
|
case CMemory::MAP_SPC7110_ROM:
|
|
return (S9xGetBasePointerSPC7110(Address));
|
|
|
|
case CMemory::MAP_C4:
|
|
return (S9xGetBasePointerC4(Address & 0xffff));
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
return (S9xGetBasePointerOBC1(Address & 0xffff));
|
|
|
|
case CMemory::MAP_NONE:
|
|
default:
|
|
return (NULL);
|
|
}
|
|
}
|
|
|
|
inline uint8 * S9xGetMemPointer (uint32 Address)
|
|
{
|
|
uint8 *GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT];
|
|
|
|
if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
|
|
return (GetAddress + (Address & 0xffff));
|
|
|
|
switch ((pint) GetAddress)
|
|
{
|
|
case CMemory::MAP_LOROM_SRAM:
|
|
if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
|
|
return (NULL);
|
|
return (Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask));
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK)
|
|
return (NULL);
|
|
return (Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB));
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK)
|
|
return (NULL);
|
|
return (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0x1f0000) >> 3)) & Memory.SRAMMask));
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
return (Memory.BWRAM - 0x6000 + (Address & 0x7fff));
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
return (Memory.SRAM + (Address & 0xffff));
|
|
|
|
case CMemory::MAP_SPC7110_ROM:
|
|
return (S9xGetBasePointerSPC7110(Address) + (Address & 0xffff));
|
|
|
|
case CMemory::MAP_C4:
|
|
return (S9xGetMemPointerC4(Address & 0xffff));
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
return (S9xGetMemPointerOBC1(Address & 0xffff));
|
|
|
|
case CMemory::MAP_NONE:
|
|
default:
|
|
return (NULL);
|
|
}
|
|
}
|
|
|
|
#endif
|